1. Field of Invention
The present invention relates to a memory slot installation. More particularly, the present invention relates to a memory slot installation that provides a constant loading for the signaling line of a computer main board despite putting in a variable amount of memory modules into the memory slots.
2. Description of Related Art
Most personal computers are assembled systems composing of a main board, interface cards and peripheral devices. The main board is the "heart" of the computer system. Besides having a central processing unit (CPU), a chip set and a series of slots for installing interface cards, the main board also has a plurality of memory slots for installing the required number memory modules depending on user's need. Each memory module can consist of one or more memory chips, which are connected together as a package. Because the number of memory modules installed in a particular main board is uncertain, designer of main boards and chip sets must consider the possibility of having a different number of memory modules installed so that its effects of loading variation on normal computer system functions are reduced to a minimum.
Since each memory module requires a driving current and a certain power rating, designers must keep in mind the driving capability of a signaling line when different number of memory modules are in use. In other words, the maximum current capable of being generated by the signaling line is an important consideration. Obviously, when only one memory module is installed, necessary driving current in the signaling line is very small. However, as more memory modules are installed, larger and larger driving current is needed. When all the memory slots are occupied by memory modules, the largest driving current is necessary.
Driving current for the memory modules in a main board is provided by the chip set. Therefore, the designer of computer chip sets must allow for situations where different combinations of memory modules are in used in the system, and then determine an appropriate driving capability. Having a driving capability too small or too large is going to affect the operation of the computer system adversely. For example, if the designed driving capability is small, whenever a greater number of memory modules are installed, there will be insufficient driving capability. This will lead to an additional timing delay in the rising edge and/or the falling edge of a signal, and thus the timing specification might be violated. However, if a larger driving capability is used in the design, and supposing there is only one memory module installed, the driving capability will then be too strong. A strong driving capability will lead to the overshooting of signal in its rising edge, undershooting of signal in its falling edge as well as causing a ringing effect. The occurrence of these phenomenal will distort the signal quality and leading to potential signal integrity issues in the main board, thereby results is the instability of the computer system itself.
When the clocking frequency in the computer system is low, the aforementioned signal distortion is going to be weak and can almost be ignored. However, as the system frequency used in the central processing unit and the main board is getting higher and higher, signal distortion problem caused by inappropriate driving capability will be intensified. Therefore, to determine the correct driving capability in the chip set has become a challenge for the designers.
Conventionally, to resolve the signal distortion problem due to inappropriate driving capability produced by a particular chip set design, two methods are used. In the first conventional method, the driving capability produced by a chip set is determined according to the power needed in a fully loaded situation. In other words, the chip set is designed to supply the power necessary for driving all the memory slots when all the memory modules are plugged. Then, a resistor having a fixed value is added to increase the loading; hence, decrease the driving capability. With this arrangement, if only a few memory modules are installed, in other words, a light load is used, the driving capability will be sufficiently depressed to avoid the overshooting or undershooting as well as the ringing effect of signals.
In the second conventional method, a buffer is also incorporated into the design of the chip set. The buffer is so designed that the driving capability is automatically adjusted by BIOS (Basic Input Output System) according to the size of the load being sensed. In other words, the chip set is able to lower the driving capability when a small number of memory modules are installed, and also able to raise the driving capability when a large number of memory modules are installed. However, due to design complication, usually a buffer with only two levels of driving capability is implemented. That means, either a level having a low driving capability is used. Or else, a level having a higher driving capability is used.
Although the above two methods are capable of reducing distortion of signals due to a variation of driving capability demanded, they have defects.
The first method of providing sufficiently large driving capability to drive a full load and then lowering the driving capability back to a lower level with the addition of a fixed resistance resistor is able to lessen the driving capability when a light load is used. However, this method of design seems to be self-contradictory. Moreover, the driving capability produced by this method is imprecise.
In the second method, a buffer is used to adjust the driving capability according to the load condition. However, the buffer will increase the complexity of chip set design and bring production costs up. Therefore, in general, only two levels of driving capability can be provided, which is still a long way from providing full load matching necessary for obtaining the optimum results.
When the clock frequency used in a computer is low, each clock cycle for a clocked signal is long. Therefore, the effect of a poor signal quality or signal distortion is only mild, and two levels of driving capability may be sufficient to solve the problem. However, with the ever-increasing clocking frequency, each clock cycle in a clocked system becomes shorter, and hence the tolerance for distorted signals becomes smaller. The two rough-and-ready methods mentioned above will be insufficient to improve the quality of signals.
In light of the foregoing, there is a need to provide an improved memory slot design so that the driving current supplied by the chip set will directly reflect the actual memory loading condition in the memory slots.